MSc Dissertation: Yann Tremeac


Adobe-PDF-downloadTremeac, Yann. Top-Down Design of DSP Systems: A Case Study. MSc Dissertation. Department of Electrical Engineering, University of Cape Town, 1999.



The primary goal of this thesis is to investigate the use of a formal top-down methodology for designing digital signal processing systems. As a case study, the design of a synthetic aperture radar (SAR) digital preprocessor is attempted. The preprocessor is targeted for the Texas Instruments’ TMS320C80 DSP. In other work linked to this project, the same preprocessor was implemented by Grant Carter on a field programmable gate array (FPGA) [2]. Secondary goals of this thesis are to document the various tools and techniques used to accelerate prototyping, and to compare the DSP and the FPGA implementation. The proposed methodology starts with the client specifications to create an initial abstract decomposition of the application. This model is then refined until the final design is obtained. The development process is broken down into four steps: the specification, the functional design (preliminary hardware-independent design), the implementation definition (detailed hardware-dependent design) and the implementation steps. A successful implementation is shown to follow from this process. The case study experience shows that the top-down approach undoubtedly has its advantages for designing DSP systems, although it must be accompanied by bottom-up principles. One of the advantages is that more emphasis is placed at design level and that the designer is initially forced to think about the solution in a hardware-independent way. Thus, the designer is more likely to produce reusable specifications and solutions of general applicability. The use of C as the programming language definitely increased the programmer productivity, as opposed to Assembler. The C80 multitasking operating system also helped in the transition from functional to executive model. However, the use of both C and the multitasking operating system has an execution time cost that cannot precisely be evaluated. This constitutes a major drawback: it means that algorithm complexity (i.e. the number of mathematical operations involved) must be evaluated at functional design level and that the DSP must be chosen with speed and memory capabilities largely superior to the algorithm complexity evaluation. In our case, the ratio between the time based on the algorithm complexity evaluation and the actual program execution time is approximately one to three. Some comparisons have been carried out with the FPGA’s implementation [2]. The specification and functional design steps lead to similar results, but major differences exist in the hardware-dependent design. Generally speaking, the implementation of a system in an FPGA implies working at a less abstract level than the mapping of a functional design onto a DSP.


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