Field-programmable gate arrays, or FPGAs, provide an attractive computing platform for software-defined radio applications. Their reconfigurable nature allows many digital signal processing (DSP) algorithms to be highly parallelised within the FPGA fabric, while their customisable I/O interfaces allow simple interfacing to analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). However, FPGA boards that deliver sufficient performance to be useful in real-world applications are generally expensive. These high prices act as a barrier to entry to FPGA systems for smaller development teams and research groups.
In order to overcome this barrier, Rhino was developed. Rhino is an FPGA-based hardware processing platform that primarily supports software-defined radio applications. The goal of Rhino is to aid research and training in smaller university research groups and development teams with limited budgets. Rhino therefore aims to provide sufficient performance to be useful, while keeping the costs low.
The architecture for Rhino was designed so that it would best serve three target applications: radar, radio astronomy and bioinformatics. The architecture centres around a Xilinx Spartan-6 FPGA connected to an AM3517 ARM processor via a parallel bus. The FPGA is used for processing computationally-intensive algorithms, such as DSP operations for radar or matrix calculations for bioinformatics. The processor is used for coordinating the flow of data in and out of the FPGA, as well as for configuring the FPGA. The FPGA connects to ADC/DAC daughterboards using industry-standard FMC connectors. The FPGA can stream the data off the board via two 10Gbps Ethernet links, or buffer it in its 512MB of DDR3 SDRAM. A 1Gbps Ethernet link is also provided.
The processor runs BORPH, a Linux variant that allows users to communicate with the FPGA via the operating system’s filesystem. The processor has a 100Mbps Ethernet link that allows users to access the board remotely and copy files to the processor over the network. The processor is supplied with 256MB of DDR2 SDRAM, and is able to boot from NAND flash memory, an SD card or from a network server. It also has USB host ports, a real-time clock and audio and video interfaces. The clocks on multiple Rhino boards can be synchronised to within 10ns of each other using the Precision Time Protocol, which runs over the Ethernet link. The entire board is monitored using power and temperature sensors.
The design of the manufactured Rhino board was verified using special test software and gateware. The board passed all software-based tests, proving that it performs as expected. Unfortunately, the FMC interface could only be tested at reduced speed, as no high-speed test hardware was available. The final cost estimate for a complete Rhino system is under $1700, cheaper than similar FPGA boards that deliver much lower performance.