Neemat, Sharef. Design and Implementation of a Digital Real-Time Secondary Surveillance Radar/Identification Friend or Foe Target Emulator. MSc Dissertation. Department of Electrical Engineering, University of Cape Town, 2010.
SSR/IFF interrogator signal processors are typically required to identify replies from up to 1500 target transponders per antenna rotation.
A real live test involving such a large number of targets would be extremely expensive, and difficult to repeat. There is thus a need for specialized target emulators to be developed and used as laboratory test equipment.
This thesis describes the design and implementation of a transistor-transistorlogic (TTL) real-time SSRlIFF target emulator. User requirements that describe the system are captured and analyzed, resulting in the generation of a system breakdown structure; a summary of the relevant concepts and requirements allocation process for each subsystem is presented, in order to produce a technical specification for the system.
The developed target emulator runs on the Innovative Integration Quixote board, and is capable of generating SSRlIFF replies for modes 1, 2, 3/A, C and secure mode 4 from up to 4000 emulated mobile targets at ranges from 0 to 600km. On the Quixote, a Xilinx Virtexll FPGA implements real-time aspects of the design, while target configuration information is continuously maintained by a Texas Instruments TMS320C6416 DSP for each antenna rotation. Emulated target configuration parameters are fully reconfigurable onthefly in terms of range, azimuth and reply codes in order to allow the user to create numerous test scenarios.
The operation of the target emulator has been verified against all design requirements, and it has been found to be compliant. The verification was performed using co-simulation and on-target testing methods. The Quixote board is a suitable HW platform for the system; however, it has been recommended that a lower cost board should be used in the future.