MSc Dissertation: Paul Archer


Adobe-PDF-downloadArcher, Paul J. A Transputer Based Implementation of a Quick Look Processor for an Airborne SAR System. MSc Dissertation. Department of Electrical Engineering, University of Cape Town, 1997.



The purpose of this thesis is to describe the development of a transputer-based real-time Synthetic Aperture Radar (SAR) processor called the Quick Look Processor (QLP). The QLP is required to produce medium resolution, real-time images at a wavelength of 2.5m for the airborne South African SAR (SASAR) system which is under development at the University of Cape Town (UCT). The required azimuth for the QLP is 30m and the system is required to process 2048 range bins at a rate of 39 range lines per second.

The algorithm used was developed at UCT, and works on the principle of dividing up the synthetic aperture into subapertures with appropriate phase corrections. This method is used in order to reduce computational loading (for real-time processing), but at the same time achieve medium resolution processing. One of the fundamental issues concerning this algorithm is its efficiency as the required azimuth resolution is increased.

The system is designed around a host PC and a network of nine transputers. The host PC communicates with the other SASAR subsystems via an Ethernet network. It is responsible for displaying and saving the SAR image, receiving and displaying geocoding information and configuring the transputer network. The transputer network is responsible for processing the SAR data. The network is connected in a pipeline configuration with a master transputer controlling the other eight slave transputers. Each slave transputer concurrently processes a section of the swath width. This method allows for easy scalability.

Once implemented, it was found that the system operated at 25% of its expected performance. This expected performance was based on a set of assumptions which were initially made aout the transputers’ performance with the QLP algorithm. After further investigation, it was found that the time taken to address data in memory had been neglected, as had the delay associated with calculating the address of a particular byte of data in an array. For example, instead of taking 0.35 microseconds to do an addition, it takes 3.1 microseconds to do an addition of two numbers stored in a 2-dimensional array while returning the result to another 2-dimensional array. Once this was considered, it was understood why the transputer performance was poor. The performance of the host PC was however found to be sufficient.

In order to process the data in real-time according to the given specifications, four times as many transputers would be required, or a different hardware platform to replace the transputer technology.



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