This thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The design of the board was done by Michael Aitken and resulted in a hardware platform with limited testing completed and limited functionality available to users. The original aim of this project was to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment. The intention was to create a seamless environment to allow scientists to utilize the ACE1 resources in a simple, consistent and efficient manner by pulling together a variety of software and hardware from a number of sources. An overview of the board is the starting point, with a review of some of the requirements that contributed to the final design. Following the overview are the efforts that went into setting up and subsequently debugging the interface that connects the coprocessor daughtercard to the host server. The challenges faced include: problems with the power network, the edge connectors and finally, timing problems with the primary protocol which prevented host-based communications.
From this point the project diverges and the options include allowing the daughtercard to function in a stand-alone fashion and we present a gateware solution for assisting users in utilizing the networking interfaces found on the daughtercard. We present our gateware options such that users can select from a number of alternatives available for each of the layers in the Open Systems Interconnect networking model. As time constraints did not allow for a complete conversion to a stand-alone processing board, we outline the future steps required to make the most of the sizeable investment in ACE1.
The alternative to utilizing ACE1 as a stand-alone processing board is to re-work the daughtercard, taking into account some of the new products and tools that have arrived in the FPGA co-processing market place since the design of ACE1 was finalized. We provide reviews of these products which clearly show the direction that the industry has taken in designing host-based co-processor systems. Some of the re-work issues were already understood at the time that Michael Aitken concluded his contribution to the ACE1 project and were presented as future work. When looking at the option of creating a second version of the co-processor board we provide a few newer ideas, sparked by the advances in the partial reconfiguration toolchains, that we discuss and recommend.