The VMEbus1 is an industry-standard high-performance bus that supports 8-, 16- and 32-bit data transfers over a non-multiplexed non-multiplexed 32-bit data bus. Additionally, VMEbus supports 16-, 24- and 32-bit addressing over a separate 32-bit address bus. The main features of VMEbus are:
- A high-speed asynchronous data bus to transfer 8-, 16- or 32-bits at a time;
- Four buses/subbuses: data transfer, arbitration, priority interrupt and utilities buses;
- Supports several bus controllers, such as central processing unit (CPU), direct memory access (DMA), input/output (I/O), and any other device that needs to control the bus. The arbitration bus avoids conflicts;
- Priority-interrupt buses where devices can request services from a VME interrupt handler;
- A utililies bus which provides power distribution, clocks, initialization and failure detection.
The purpose of this dissertation is to describe a project intended for design and implementation of a reconfigurable VME exerciser2 at iThemba Laboratory for Accelerator-Based Science (iThemba LABS)3. This is realized by providing a design and implementation of VME printed circuit board (PCB) as the main board, hardware description language (HDL) for VME daughter-card and finally, the graphical user interface (GUI) is designed and implemented as well. Next, these designs are tested to verify that they conform to the specified user requirements. From the results, this project project proves to meet the user requirements, hence it can be said that it was successful. In addition to meeting user requirements, data rates of up to 26 Megabytes per second (MBPS) were realized.